The technology of Direct Rambus DRAM provides an entirely new approach to the architecture of the memory subsystem.

Firstly, a special interface is developed for connecting memory modules to the controller. Secondly, the memory modules are connected to the controller with special channels with a width of data bus 18 (16 +2) bits and the control bus of 8 bits. Thirdly, new memory modules RIMM (Rambus InLine Memory Module) are developed.
Each channel can support up to 32 banks and can theoretically operate at a frequency of 800 MHz. Operating frequency is set by its own generator of the memory subsystem. Thus, a part of the memory subsystem operates independently of the clock frequencies of the remaining components of the motherboard.

Several channels can be connected to the controller. The controller operates at a frequency of 200 MHz, which is now determined by FSB.
The volume of commercially available modules DRAM is 64, 128 and 256 MB in the future the products to 1 GB are expected. Since the use of 9-th bit in each byte of data is left to the discretion of the manufacturer, some firms enter the ESS function, increase the capacity of other chips. In the latter case there are modules with capacity 72, 144 or 288 MB.

Today DR RAM clock frequency is 400 MHz, but the data is transmitted on both fronts of the signal, so one can assume that the exchange rate is doubled and reaches 800 MHz. If the controller is connected by to two channels, theoretical peak capacity is up to 3.2 Gbps. But this figure is achievable only in theory and massive amounts of data.

On practice, shortcomings of technology associated with its architecture begin to manifest. For example, if the write data must follow the read operations, the controller has to generate the delay, whose value depends on the physical length of wire channel. If the channel is short, the delay will be only one step (at 400 MHz about 2.5 ns). In the worst case, with a maximum length channel delay the value reaches 12.5 ns. To this we must add the delay generated in the own read / write cycles, so the grand total looks are not so rosy, even in comparison with the modules SDRAM.

Other disabilities, critical to the user, are invented by the manufacturers mode power management modules. If the supply voltage 2,5 V has become almost standard for all new technologies of DRAM, it modes Active , Standby, NAP and PowerDown. The most interesting thing that a chip doesn’t share in the current data to the controller, it is automatically put on hold, otherwise the overheating of the system is possible, as clock speeds are very high. At the same a switch from Standby mode to an active state requires 100 ns!

Memory microchips of RIMM modules are forced to shut down by the sleeve due to problems with electromagnetic induction and the intense heat.
We should pay tribute to the engineers: responding to criticism, they took the so-called “initiative 4i” This program reduces the number of banks in the DR DRAM chips, all of them become independent. In addition, thermal parameters of RIMM modules have been improved. In fairness, we note that the power of specialized memory systems has proved itself well. In particular, six-channel system of DRAM memory with a peak capacity of 3 GB / sec is used at graphic stations. Today, memory RIMM is commercially available, working with the original 133 MHz, and the effective frequency is 1066 MHz!

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